Increasing demand for high definition TV products, including interactive TV in a HD format and HD video compression encoding and decoding, requires increasing sophistication, flexibility, and performance in the supporting electronics. The sophistication, flexibility, and performance requirements for HD digital video processing, exceeds the capabilities of current generations of processor architectures by, in many cases, orders of magnitude.
The demands of video encoding for HD formats are both memory and data processing intensive, requiring efficient and high bandwidth memory organizations coupled with compute intensive capabilities. In addition, a video encoding product must be capable of supporting multiple standards each of which includes multiple optional features which can be supported to improve image quality and further reductions in compression bandwidth. Due to these multiple demands, a flexible parallel processing approach must be found to meet the demands in a cost effective manner.
A number of algorithmic capabilities are generally common between multiple video encoding standards, such as MPEG-2, H.264, and SMPTE-VC-1. Motion estimation/compensation and deblocking filtering are two examples of general algorithms that are required for video encoding. To efficiently support motion estimation algorithms and other complex programmable functions which may vary in requirements across the multiple standards, a processor by itself would require significant parallelism and very high clock rates to meet the requirements. A processor of this capability would be difficult to develop in a cost effective manner for commercial products.
A digital video sequence consists of a series of pictures (combined luminance and chrominance samples) arranged in a temporal succession. It may contain either progressive or interlaced frames, which may be mixed together within the same video stream.
Motion estimation/compensation methods used by video coding algorithms exploit this temporal picture structure by reducing the redundancy inherent in the video sequences of this type. They represent a central part of the video encoding process of MPEG-4 AVC H.264 and SMPTE-VC-1 video encoding standards.
Motion estimation is computationally the most expensive part of a video encoding process. On average it takes about 60-80% of the total available computational time, thus having the highest impact on the speed of the overall encoding process. It also has a major impact on the visual quality of encoded video sequences.
The most common motion estimation algorithms are block matching algorithms operating in the time domain. Here motion vectors are used to describe the best temporal prediction for a current block of pixels to be encoded. A time domain prediction error between the current block of pixels and the reference block of pixels is formed, and a search is performed to minimize this value. In general, motion search is divided up into a first full pixel search, followed by a half pixel refined search which is followed by a quarter pixel search.
The motion search process is computationally intensive and represents a bottleneck in efficient real-time execution of video encoding at high definition formats.
It will be highly advantageous to efficiently address such problems as the quarter pixel search process discussed in greater detail below.